1. Field of the Invention
The invention relates to a semiconductor memory device and a method of testing the same.
2. Description of Related Art
A typical semiconductor memory device is constituted by a plurality of memory cells. After the semiconductor memory device is completely formed and before the device is packaged, the device needs to be inspected in order to find defective memory cells. In a method of testing the typical memory device, certain data patterns “0” and “1” are written into each of the memory cells, and data stored in the memory cells are read, so as to detect any unexpected value.
FIG. 1 is a schematic view illustrating the structure of a conventional semiconductor memory device 10. With reference to FIG. 1, the semiconductor memory device 10 includes a plurality of pairs of bit lines, a plurality of word lines WL[0], WL[1], and WL[2], and a plurality of memory cells MC placed at crossing positions of the bit lines and the word lines. Each pair of the bit lines is constructed of one bit line BL and one complementary bit line /BL. The semiconductor memory device 10 further includes a command/address controller 11, a sensing signal generating circuit 12, a row decoder 14, a column decoder 16, a sensing amplifier unit 18, and a pre-charging circuit unit 19. The sensing amplifier unit 18 and the pre-charging circuit unit 19 are coupled to the pairs of bit lines.
FIG. 2 is a timing diagram illustrating that the semiconductor memory device 10 is operated in a test mode. With reference to FIG. 1 and FIG. 2, after the command/address controller 11 in the semiconductor memory device 10 receives a first activate command CMD1 that synchronizes with an external clock signal XCLK, the row decoder 14 activates a first word line WL[0], so as to turn on the memory cells into which the data are to be written. After the first word line WL[0] is activated, the sensing signal generating circuit 12 outputs a sensing enabling signal SAE at the logic high level, so as to activate the sensing amplifier unit 18 and deactivate the pre-charging circuit unit 19. Next, the command/address controller 11 receives N write commands CMD2 to generate N column selection signals and transfer the N column selection signals to the column decoder 16. The column decoder 16 sequentially writes the test data into the memory cells MC coupled to the first word line WL[0] based on the column selection signals.
After the test data are written into the memory cells MC, the command/address controller 11 receives a pre-charge command CMD3 to deactivate the first word line WL[0]. After the first word line WL[0] is deactivated, the sensing signal generating circuit 12 outputs the sensing enabling signal SAE at the logic low level, so as to deactivate the sensing amplifier unit 18 and activate the pre-charging circuit unit 19. Hence, a pre-charging voltage lower than a power voltage is applied between each pair of bit lines.
In order to write the test data into the memory cells MC coupled to other word lines, the above-mentioned steps should be repeated in the semiconductor memory device 10, e.g., steps of activating a second word line WL[1], generating N column selection signals to sequentially write the test data into a selected pair of bit lines, deactivating the second word line WL[1], and pre-charging the pair of bit lines. As the number of the pairs of bit lines and the number of the word lines increases, significant time is required for writing the test data into all of the memory cells MC in the semiconductor memory device 10.
Therefore, a semiconductor memory device and a method of testing the same are necessary in order to effectively reduce the time of writing the test data into the semiconductor memory device.